1. Field of the Invention
The invention relates to improvements in cache control in a data processing system which enables the processor and main storage to concurrently access the cache at their highest data transfer rates without conflict.
2. Description Of The Prior Art
In the prior art, U.S. Pat. No. 3,705,388 interrupts main storage while it is transferring a line of data to a cache to permit a processor to access a different line of data in the cache. U.S. Pat. Nos. 3,670,307 and 3,670,309 enable concurrent processor and line fetch accesses by accessing different BSM's in the cache; that is, the processor can access the busses of one BSM of a cache concurrently with a line fetch from main storage accessing the different busses of another BSM of the cache, which must be constructed with plural BSM's. U.S. Pat. No. 3,588,829 delays a processor request to the cache from the first word of a line transfer until after the last word of the line fetch is completed from main storage to the cache. U.S. Pat. No. 3,806,888 provides fast readout means in the main memory so that on each line of data can be transferred through a buffer to a cache in the time normally required to transfer a word from main memory. None of these prior patents reveal the concept involved in the subject invention which enables a cache to concurrently be accessed by main storage and a processor at their maximum rates without interferring with each other and without added buffers, and without interrupting either the main storage or processor operations.